A Testable Design Method for Memories by Boundary Scan Technique
نویسندگان
چکیده
منابع مشابه
Non-scan design for testable data paths using thru operation
| We present a new non-scan DFT technique for register-transfer (RT) level data paths. In the technique, we add thru operations to some operational modules to make the data path easily testable. We de ne a testable measure, weak testability, and consider the problem to make the data path weakly testable with minimum hardware overhead. We also de ne a measure to estimate the test generation time...
متن کاملTestable Design and Testing of MCMs Based on Multifrequency Scan
In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to ofSer the necessity of controllability and observability. Part of the boundary scan cells used in the chip le...
متن کاملA Boundary Meshless Method for Neumann Problem
Boundary integral equations (BIE) are reformulations of boundary value problems for partial differential equations. There is a plethora of research on numerical methods for all types of these equations such as solving by discretization which includes numerical integration. In this paper, the Neumann problem is reformulated to a BIE, and then moving least squares as a meshless method is describe...
متن کاملBoundary Scan Test for FPGA-Based Embedded Design
FPGAs allow designers to implement an increasing proportion of an embedded design in a small number of reconfigurable components. It is quite normal to take advantage of the FPGA’s reconfigurability to download test programs to exercise various parts of the system and to perform self-test routines in the field. During development and prototyping, however, engineers must debug hardware before fu...
متن کاملBoundary - scan design principles for efficient LSSD ASIC testing
A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products. This technique permits comprehensive testing of LSSD ASlCs with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic test equipment (ATE). This paper describe...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ITM Web of Conferences
سال: 2016
ISSN: 2271-2097
DOI: 10.1051/itmconf/20160704006